Tracing the activity of a data processing system whereby a stream of trace data is generated including data representing the step-by-step activity within the system is a highly useful tool in system development. As well as off-chip tracing mechanisms for capturing and analyzing trace data, increased amounts of tracing functionality are being placed on-chip. An example of such on-chip tracing mechanisms is the Embedded Trace Macrocell (ETM) provided by ARM Limited, Cambridge, England in association with various of their ARM processors.
Such tracing mechanisms produce in real time a stream of trace elements representing activities of the data processing system that are desired to be traced. This trace stream can then subsequently be used to facilitate debugging of sequences of processing instructions being executed by the data processing system.
Within a System-on-Chip (SoC) there will typically be a number of master devices interconnected with a number of slave devices via one or more buses. Transactions are typically initiated by the master devices and are actioned by appropriate slave devices. These transactions are routed over the interconnecting bus network. Whilst the ETM allows a great deal of trace data to be generated concerning the activities of the associated processor core (a processor core being an example of a master device), the ETM is unable to trace information about the actual transactions being routed from that processor core, or indeed from other master devices, onto the bus.
As SoC designs increase in complexity, so the complexity of the interconnecting bus network increases. It is known to develop monitor logic to monitor a bus, but as bus designs increase in complexity, the complexity and size of the associated monitor logic increases. Nevertheless, the ability to monitor the activities of the bus in order to produce trace data relating to those activities that can then subsequently be used (possibly in combination with any trace data produced by an ETM) to debug sequences of processing instructions is highly desirable.
Accordingly, it would be desirable to provide functionality that allowed tracing of attributes associated with transactions initiated from the master device to the bus without significantly increasing the cost and complexity of the system design.